High speed memory access, and reduced power consumption are features that are demanded from semiconductor devices. In recent years, a computer system that adopted multi-core processors and simultaneous execution of a plurality of applications has resulted in lower spatial locality of access patterns to a memory device serving as a main memory (e.g., dynamic random access memory (DRAM)) and more random access patterns. A typical access pattern to the DRAM repeats bank activation, read access or write access, and bank precharge in the order. When different banks are continuously accessed by bank interleaving using the access pattern mentioned above, simultaneous bank activation to the different banks may cause peak power consumption to exceed an acceptable threshold. In order to avoid such excess power consumption, a number of banks to be accessed simultaneously may be limited (e.g., maximum of four). However, the limitation of the number of banks to be accessed may lower access efficiency of the DRAM.
Some techniques to reduce the activation/precharge power consumption have been disclosed. For example, Cooper-Balis and Jacob proposed a fine-grained activation technique that uses an additive latency and a posted column-address strobe (posted-CAS) command to acquire a column address to be accessed while a bank is active. Word lines having a length shorter than ordinary word lines including the column address may be activated only with a corresponding sense amplifier. In this manner, power consumption while the bank is active may be reduced. However, the fine-grained activation technique may induce severe performance or area overhead due to a reduced data bandwidth. Zhang, et al. discloses a Half-DRAM technique that avoids a bandwidth reduction of data to address the problems of the fine-grain activation technique of Cooper-Balis and Jacob. The Half-DRAM technique enables the fine-grained activation with full data bandwidth by leveraging the “1RD-2HFF” structure and by exploiting sub-array level parallelism.
In another example, sub word line drivers of the DRAM may be in a staggered arrangement in column segments. FIG. 1 is a schematic diagram of column segments in an example dynamic random-access memory (DRAM). One block is divided into a plurality of column segments that may be matrices MAT0 to MAT7. Sub word line drivers are disposed between the respective matrices and on upper and lower sides of the block. For example, FIG. 1 shows a configuration in which column addresses Y9 and Y8 are used as column segments. Each block is divided into four column segments, where each column segment includes two matrices and a corresponding sub word line is selected and activated. Due to a small pitch of the sub word lines, a sub word line driver layout includes the sub word line drivers with a pitch twice as large as the pitch of the sub word lines. As shown in FIG. 1, a sub word line selection range selected by using Y9 and Y8 may correspond to one column segment. For example, the sub word line selection range may be two rows of the sub word line drivers respectively disposed between MAT1 and MAT2, between the MAT3 and MAT4, as well as between the MAT5 and MAT6, in order to keep each sub word line length. This configuration of having two rows of the sub word line drivers at three locations in each block, however, may increase a chip area.